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CD chip designs govern the capacity of their buckets. The two designs most commonly seen are the full-frame sensor and the interline chip. The first, the full-frame sensor (Figure 3), is a straightforward array of pixels of various capacities (well depth), and widths (pixel size). The other design, the interline chip, introduces a feature that is beneficial in the transfer rate but limits the pixel size. The interline chip, although also laid out as an array of pixels, includes transfer sections located next to each row of pixels. Due to its layout, the parameters of each pixel are restricted. It is easy to see the limitations of the bucket size in the architecture of the interline chip. Construction of a megapixel CCD chip with pixels adequately large for high-quality data acquisition is technically possible; however, the chip would be very large and there fore very expensive. As a result, such a chip is not being offered commercially.

Once charge has accumulated within the pixels, it is transferre d out of the pixels for conversion into data. An analog-to-digital converter, or digitizer, translates the number of electro n s into digital numerical data. The digitizer determines the bit number of the output. That is, a 12-bit digitizer will produce a 12-bit image and a 16-bit digitizer a 16-bit image. To ensure accurate data collection, it is crucial to select a digitizer that appropriately matches the well depth of the pixels. For a 12-bit digitizer with 4,096 levels, the best well depth would have a capacity of 4,096 electrons; that is, for each collected electron, the data would correspond literally to a gray level. For example, if a pixel contained 2,000 electrons, the digital readout would be at the 2,000th
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