Self-assembled nanowires could make chips smaller ...( CHAMPAIGN Ill. Researchers at the U...)

CHAMPAIGN, Ill. Researchers at the University of Illinois have found a new way to make transistors smaller and faster. The technique uses self-assembled, self-aligned, and defect-free nanowire channels made of gallium arsenide.

In a paper to appear in the IEEE (Institute of Electrical and Electronics Engineers) journal Electron Device Letters, U. of I. electrical and computer engineering professor Xiuling Li and graduate research assistant Seth Fortuna describe the first metal-semiconductor field-effect transistor fabricated with a self-assembled, planar gallium-arsenide nanowire channel.

Nanowires are attractive building blocks for both electronics and photonics applications. Compound semiconductor nanowires, such as gallium arsenide, are especially desirable because of their better transport properties and versatile heterojunctions. However, a number of challenges including integration with existing microelectronics must first be overcome.

"Our new planar growth process creates self-aligned, defect-free gallium-arsenide nanowires that could readily be scaled up for manufacturing purposes," said Li, who also is affiliated with the university's Micro and Nanoelectronics Laboratory and the Beckman Institute. "It's a non-lithographic process that can precisely control the nanowire dimension and orientation, yet is compatible with existing circuit design and fabrication technology."

The gallium-arsenide nanowire channel used in the researchers' demonstration transistor was grown by metal organic chemical vapor deposition using gold as a catalyst. The rest of the transistor was made with conventional microfabrication techniques.

While the diameter of the transistor's nanowire channel was approximately 200 nanometers, nanowires with diameters as small as 5 nanometers can be made with the gold-catalyzed growth technique, the researchers report. The self-aligned orientation of the nanowires is determined by the crystal
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