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SRC and UCLA advance design-dependent process monitoring for semiconductor wafer manufacturing
Date:5/25/2011

especially useful in early stages of yield ramp for a product. An early version of this work appeared in the International Conference on Computer-Aided Design in 2010.

"The notion of design-assisted manufacturing is a big change from the way things are done currently," said Puneet Gupta, professor of electrical engineering at UCLA who is also a SRC alumni student. "Our research provides the industry a way to not waste resources in producing silicon wafers that will eventually lose money because chips on them are not good enough for production. We believe that the cost reductions from this and other design-assisted manufacturing methods that we are investigating could easily be as much as one full technology node."

Along with semiconductor foundries, design houses would also benefit from wafer-cost reductions achieved through the design-dependent process monitoring approach. Researchers are fine-tuning the approach-including finalizing results from a 45 nanometer silicon prototype effort-and hope to see the industry begin implementing the process within the next few years.

"The semiconductor industry has been heavily focused on purely technological solutions to scaling, and we've barely scratched the surface on the potential of design-assisted technology scaling," said Bill Joyner, SRC director of Computer-Aided Design and Test. "This research leverages design information meaningfully and practically to reduce process control requirements and manufacturing costs."


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Contact: Wileen Wong Kromhout
wwkromhout@support.ucla.edu
University of California - Los Angeles
Source:Eurekalert

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