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es to be used as interconnects in integrated circuits."
The study, based on large-scale quantum simulations, was conducted using the Rensselaer Computational Center for Nanotechnology Innovations (CCNI), one of the world's most powerful university-based supercomputers.
Copper interconnects suffer from a variety of unwanted problems, which grow more prominent as the size of the interconnects shrink. Electrons travel through the copper nanowires sluggishly and generate intense heat. As a result, the electrons "drag" atoms of copper around with them. These misplaced atoms increase the copper wire's electrical resistance, and degrade the wire's ability to transport electrons. This means fewer electrons are able to pass through the copper successfully, and any lingering electrons are expressed as heat. This heat can have negative effects on both a computer chip's speed and performance.
It is generally accepted that a quality replacement for traditional copper must be discovered and perfected in the next five to 10 years in order to further perpetuate Moore's Lawan industry mantra that states the number of transistors on a computer chip, and thus the chip's speed, should double every 18 to 24 months.
Nayak's recent work, published in the journal ACS Nano, is titled "Effect of Layer Stacking on the Electronic Structure of Graphene Nanoribbons." When cut into nanoribbons, graphene is known to exhibit a band gapan energy gap between the valence and conduction bandswhich is an unattractive property for interconnects. The new study shows that stacking the graphene nanoribbons on top of each other, however, could significantly shrink this band gap. The study may be viewed online at: http://dx.doi.org/10.1021/nn200941u
"The optimal thickness is a stack of four to six layers of graphene," said Neerav Kharche, first author of the study and a computational scientist at CCNI. "Stacking mor
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| Contact: Michael Mullaney mullam@rpi.edu 518-276-6161 Rensselaer Polytechnic Institute Source:Eurekalert |
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