Technology being developed by researchers from three universities is expected to improve next-generation integrated circuits called network-on-chip. The work will support the growing demand for computing power and could improve overall performance of multi-core processors by integrating wireless technology with copper wiring on devices.
Amlan Ganguly, an assistant professor of computer engineering at Rochester Institute of Technology, is part of the team that received an $800,000 grant from the National Science Foundation for the project. He will be working with project leader Partha Pande, associate professor of electrical engineering at Washington State University, and researchers from Georgia Institute of Technology to develop the new infrastructure that could increase the speed and reduce the power usage in today's computer processors, augmenting the on-chip network of miniature copper wires with wireless interconnects.
The on-chip wireless protocol that Ganguly will develop, called "Hierarchical On-Chip Millimeter-Wave Wireless Micro-Networks for Multi-Core Systems," will allow for multiple processing engines on the chip to communicate simultaneously using a process much like that of traditional mobile telephone networks.
This first-of-its-kind process is projected to have improved results from earlier work on a token-based protocol where access on the wireless channel is granted to only a single processor one time, he says.
"The role of on-chip networks is to communicate between multiple cores, or processors, on a chip efficiently so that they can share their results and can communicate effectively with each other," Ganguly says. "That communication has been a bottleneck over the past 10 years because the communication has been taking up a lot of energy, a lot of processing time. The major thrust in this area is to reduce that energy dissipation, to make computing systems more sustainable."
On-chip networks ar
|Contact: Michelle Cometa|
Rochester Institute of Technology