Using graphene either as an alternative to, or most likely as a complementary material with silicon, offers the promise of much faster future electronics, along with several other advantages over the commonly used semiconductor. However, creating the one-atom thick sheets of carbon known as graphene in a way that could be easily integrated into mass production methods has proven difficult.
When graphene is grown, lattices of the carbon grains are formed randomly, linked together at different angles of orientation in a hexagonal network. However, when those orientations become misaligned during the growth process, defects called grain boundaries (GBs) form. These boundaries scatter the flow of electrons in graphene, a fact that is detrimental to its successful electronic performance.
Researchers Joe Lyding and Eric Pop from the University of Illinois' Beckman Institute and their research groups have now given new insight into the electronics behavior of graphene with grain boundaries that could guide fabrication methods toward lessening their effect. The researchers grew polycrystalline graphene by chemical vapor deposition (CVD), using scanning tunneling microscopy and spectroscopy for analysis, to examine at the atomic scale grain boundaries on a silicon wafer. They reported their results in the journal ACS Nano.
"We obtained information about electron scattering at the boundaries that shows it significantly limits the electronic performance compared to grain boundary free graphene," Lyding said. "Grain boundaries form during graphene growth by CVD, and, while there is much worldwide effort to minimize the occurrence of grain boundaries, they are a fact of life for now.
"For electronics you would want to be able to make it on a wafer scale. Boundary free graphene is a key goal. In the interim we have to live with the grain boundaries, so understanding them is what we're trying to do."
Lyding compared graphene lattices made wi
|Contact: Steve McGaughey|
Beckman Institute for Advanced Science and Technology