The next major advance in computer processors will likely be the move from today's two-dimensional chips to three-dimensional circuits, and the first three-dimensional synchronization circuitry is now running at 1.4 gigahertz at the University of Rochester.
Unlike past attempts at 3-D chips, the Rochester chip is not simply a number of regular processors stacked on top of one another. It was designed and built specifically to optimize all key processing functions vertically, through multiple layers of processors, the same way ordinary chips optimize functions horizontally. The design means tasks such as synchronicity, power distribution, and long-distance signaling are all fully functioning in three dimensions for the first time.
"I call it a cube now, because it's not just a chip anymore," says Eby Friedman, Distinguished Professor of Electrical and Computer Engineering at Rochester and faculty director of the pro of the processor. "This is the way computing is going to have to be done in the future. When the chips are flush against each other, they can do things you could never do with a regular 2D chip."
Friedman, working with engineering student Vasilis Pavlidis, says that many in the integrated circuit industry are talking about the limits of miniaturization, a point at which it will be impossible to pack more chips next to each other and thus limit the capabilities of future processors'. He says a number of integrated circuit designers anticipate someday expanding into the third dimension, stacking transistors on top of each other.
But with vertical expansion will come a host of difficulties, and Friedman says the key is to design a 3-D chip where all the layers interact like a single system. Friedman says getting all three levels of the 3-D chip to act in harmony is like trying to devise a traffic control system for the entire United Statesand then layering two more United States above the first and somehow getting every bit of traffic f
|Contact: Jonathan Sherwood|
University of Rochester