It also means layers of silicon-oxide memory can be stacked in tiny but capacious three-dimensional arrays. "I've been told by industry that if you're not in the 3-D memory business in four years, you're not going to be in the memory business. This is perfectly suited for that," Tour said.
Silicon-oxide memories are compatible with conventional transistor manufacturing technology, said Tour, who recently attended a workshop by the National Science Foundation and IBM on breaking the barriers to Moore's Law, which states the number of devices on a circuit doubles every 18 to 24 months.
"Manufacturers feel they can get pathways down to 10 nanometers. Flash memory is going to hit a brick wall at about 20 nanometers. But how do we get beyond that? Well, our technique is perfectly suited for sub-10-nanometer circuits," he said.
Austin tech design company PrivaTran is already bench testing a silicon-oxide chip with 1,000 memory elements built in collaboration with the Tour lab. "We're real excited about where the data is going here," said PrivaTran CEO Glenn Mortland, who is using the technology in several projects supported by the Army Research Office, National Science Foundation, Air Force Office of Scientific Research, and the Navy Space and Naval Warfare Systems Command Small Business Innovation Research (SBIR) and Small Business Technology Transfer programs.
"Our original customer funding was geared toward more high-density memories," Mortland said. "That's where most of the paying customers see this going. I think, along the way, there will be side applications in various nonvolatile configurations."
Yao had a hard time convincing his colleagues that silicon oxide alone could make a circuit. "Other group members didn't believe him," said Tour, who added that nobody recognized silicon oxide's potential, even though it's "the most-studied material in human history."
"Most people, when they saw this ef
|Contact: David Ruth|